Block Level Verification Environment:
A seperate verification environment is created for each functionally independent block on SoC. This consists of Universal Verification Components (UVCs), which are later reused as such or with some modification when verifying top level design.
This diagram shows a
typical block level Verification Environment using
UVM
System Level Verification Environment:
As shown in diagram, top level
design (SoC) may contain several blocks with interdependent
functionality. Therefore at top level the choice of reusable UVCs
is made meticulously to optimize the verification efforts. Apart
from this there may be integration of third party VIPs at top
level. Usually, scoreboard and coverage model is written seperately
for top level verification environment. Many reusable UVCs need
modification as per need.
Above diagram shows a
typical system level verification environment making reuse of UVCs
and third part VIPs